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1 of 29 september 7, 2007 ? 2007 integrated device technology, inc. *notice: the information in this document is subject to change without notice advance information idt and the idt logo are registered trademarks of integrated device technology, inc. ? device overview the 89hpes8t5a is a member of idt?s precise? family of pci express switching solutions. the pes8t5a is an 8-lane, 5-port periph- eral chip that performs pci express base switching. it provides connec- tivity and switching functions between a pci express upstream port and up to four downstream ports and supports switching between down- stream ports. features high performance pci express switch ? eight 2.5gbps pci express lanes ? five switch ports ? upstream port is x4 ? downstream ports are x1 ? low-latency cut-through switch architecture ? support for max payload sizes up to 256 bytes ? one virtual channel ? eight traffic classes ? pci express base specification revision 1.1 compliant flexible architecture with nume rous configuration options ? automatic lane reversal on all ports ? automatic polarity inversion on all lanes ? ability to load device configuration from serial eeprom legacy support ? pci compatible intx emulation ? bus locking highly integrated solution ? requires no external components ? incorporates on-chip internal memory for packet buffering and queueing ? integrates eight 2.5 gbps embedded serdes with 8b/10b encoder/decoder (no separate transceivers needed) reliability, availability, and serviceability (ras) features ? internal end-to-end parity protection on all tlps ensures data integrity even in systems that do not implement end-to-end crc (ecrc) ? supports ecrc and advanced error reporting ? supports pci express native hot-plug, hot-swap capable i/o ? compatible with hot-plug i/o expanders used on pc mother- boards power management ? utilizes advanced low-power design techniques to achieve low typical power consumption ? supports pci power management interface specification (pci- pm 1.2) ? unused serdes are disabled. ? supports advanced configuration and power interface speci- fication, revision 2.0 (acpi) supporting active link state testability and debug features ? built in pseudo-random bit stream (prbs) generator ? numerous serdes test modes ? ability to read and write any internal register via the smbus ? ability to bypass link training and force any link into any mode ? provides statistics and performance counters block diagram figure 1 internal block diagram 5-port switch core / 8 pci express lanes frame buffer route table port arbitration scheduler serdes phy logical layer mux / demux transaction layer data link layer (port 0) (port 2) serdes phy logical layer mux / demux transaction layer data link layer serdes phy logical layer mux / demux transaction layer data link layer (port 3) (port 5) serdes phy logical layer transaction layer data link layer mux / demux (port 4) serdes phy logical layer transaction layer data link layer mux / demux 89hpes8t5a data sheet advance information* 8-lane 5-port pci express? switch
2 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information 11 general purpose input/output pins ? each pin may be individually configured as an input or output ? each pin may be individually configured as an interrupt input ? some pins have selectable alternate functions packaged in a 15mm x 15mm 196-ball bga with 1mm ball spacing product description utilizing standard pci express interconnect, the pes8t5a provides the most efficient i/o connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. it provides 3 gbps (24 gbps) of aggrega ted, full-duplex switching capacity through 6 integrated serial lanes, using prov en and robust idt technology. each lane provides 2.5 gbps of ba ndwidth in both direc- tions and is fully compliant with pci express base specification revision 1.1. the pes8t5a is based on a flexible and efficient layered architectu re. the pci express layer consists of serdes, physical, data link and trans- action layers in compliance with pci express base specification revision 1.1. the pes8t5a can operate either as a store and for ward or cut-through switch and is designed to switch memory and i/o transactions. it supports eight traffic classes (tcs) and one virtual channel ( vc) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity. figure 2 i/o expansion application smbus interface the pes8t5a contains two smbus interfaces. the slave interface pr ovides full access to the configuration registers in the pes8t 5a, allowing every configuration register in the device to be read or writt en by an external agent. the master interface allows the default configuration register values of the pes8t5a to be overridden following a reset with val ues programmed in an external serial eeprom. the master interf ace is also used by an external hot-plug i/o expander. six pins make up each of the two smbus interfaces. these pins consist of an smbus clock pin, an smbus data pin, and 4 smbus add ress pins. in the slave interface, these address pins allow the smbus address to which the device responds to be configured. in the master in terface, these address pins allow the smbus address of the serial configuration eeprom from which data is loaded to be configured. the smbus a ddress is set up on negation of perstn by sampling the corresponding address pins. when the pins are sampled, the resulting address is assigned as shown in table 1. memory memory memory processor memory north bridge pes8t5a processor x1 x1 x1 x1 south bridge ge lom x4 ge lom ge 1394
3 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information as shown in figure 3, the master and slave smbuses may be used in a unified or split configurati on. in the unified configuratio n, shown in figure 3(a), the master and slave smbuses are tied together and the pes8t5a acts both as a smbus master as well as a smbus slave on th is bus. this requires that the smbus master or processor that has access to pes8t5a registers supports smbus arbitration. in some systems, t his smbus master interface may be implemented using general purpose i/o pins on a pr ocessor or micro controller, and may not support smbus arbit ration. to support these systems, the pes8t5a may be configured to operate in a split configuration as shown in figure 3(b). in the split configuration, the master and slave smbuses operat e as two independent buses and thus multi-master arbitration is never required. the pes8t5a supports reading and writing of the serial eeprom on the master smbus via the slave smbus, allowing in system progr amming of the serial eeprom. figure 3 smbus interface configuration examples hot-plug interface the pes8t5a supports pci express hot-plug on each downstream port. to reduce the number of pins required on the device, the pes 8t5a utilizes an external i/o expander, such as that used on pc mother boards, connected to the smbus master interface. following res et and configura- tion, whenever the state of a hot-plug output needs to be modi fied, the pes8t5a generates an smbus transaction to the i/o expan der with the new value of all of the outputs. whenever a hot-plug input changes, the i/o expander generates an interrupt which is received on th e ioexpintn input pin (alternate function of gpio) of the pes8t5a. in response to an i/o expander interrupt, the pes8t5a generates an smbus transacti on to read the state of all of the hot-plug inputs from the i/o expander. bit slave smbus address master smbus address 1 ssmbaddr[1] msmbaddr[1] 2 ssmbaddr[2] msmbaddr[2] 3 ssmbaddr[3] msmbaddr[3] 4 0 msmbaddr[4] 5 ssmbaddr[5] 1 61 0 71 1 table 1 master and slave smbus address assignment processor pes8t5a ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom processor pes8t5a ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom ... ... (a) unified configuration and management bus (b) split configuration and management buses
4 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information general purpose input/output the pes8t5a provides 11 general purpose input/output (gpio) pi ns that may be used by the system designer as bit i/o ports. each gpio pin may be configured independently as an input or output through softwar e control. some gpio pins are shared with other on-chip fu nctions. these alternate functions may be enabled via software, smbus sl ave interface, or serial configuration eeprom. pin description the following tables lists the functions of the pins provided on the pes8t5a. some of the functions listed may be multiplexed o nto the same pin. the active polarity of a signal is defined using a suffix. signals ending with an ?n? are defined as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses, and select li nes) will be interpreted as being active, or asserted, when at a logic one (high) level. signal type name/description pe0rp[3:0] pe0rn[3:0] i pci express port 0 serial data receive. differential pci express receive pairs for port 0. pe0tp[3:0] pe0tn[3:0] o pci express port 0 serial data transmit. differential pci express trans- mit pairs for port 0. pe2rp[0] pe2rn[0] i pci express port 2 serial data receive. differential pci express receive pair for port 2. pe2tp[0] pe2tn[0] o pci express port 2 serial data transmit. differential pci express trans- mit pair for port 2. pe3rp[0] pe3rn[0] i pci express port 3 serial data receive. differential pci express receive pair for port 3. pe3tp[0] pe3tn[0] o pci express port 3 serial data transmit. differential pci express trans- mit pair for port 3. pe4rp[0] pe4rn[0] i pci express port 4 serial data receive. differential pci express receive pair for port 4. pe4tp[0] pe4tn[0] o pci express port 4 serial data transmit. differential pci express trans- mit pair for port 4. pe5rp[0] pe5rn[0] i pci express port 5 serial data receive. differential pci express receive pair for port 5. pe5tp[0] pe5tn[0] o pci express port 5 serial data transmit. differential pci express trans- mit pair for port 5. perefclkp perefclkn i pci express reference clock. differential reference clock pair input. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic and on-chip serdes. the frequency of the dif- ferential reference clock is determined by the refclkm signal. refclkm i pci express reference clock mode select. this signal selects the fre- quency of the reference clock input. 0x0 - 100 mhz 0x1 - 125 mhz table 2 pci express interface pins
5 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information signal type name/description msmbaddr[4:1] i master smbus address. these pins determine the smbus address of the serial eeprom from which configuration information is loaded. msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus. msmbdat i/o master smbus data. this bidirectional signal is used for data on the mas- ter smbus. ssmbaddr[5,3:1] i slave smbus address. these pins determine the smbus address to which the slave smbus interface responds. ssmbclk i/o slave smbus clock. this bidirectional signal is used to synchronize trans- fers on the slave smbus. ssmbdat i/o slave smbus data. this bidirectional signal is used for data on the slave smbus. table 3 smbus interface pins signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p2rstn alternate function pin type: output alternate function: reset output for downstream port 2 gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p4rstn alternate function pin type: output alternate function: reset output for downstream port 4 gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn0 alternate function pin type: input alternate function: i/o expander interrupt 0 input gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn1 alternate function pin type: input alternate function: i/o expander interrupt 1 input gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn2 alternate function pin type: input alternate function: i/o expander interrupt 2 input gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. table 4 general purpose i/o pins (part 1 of 2)
6 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: gpen alternate function pin type: output alternate function: general purpose event (gpe) output gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p3rstn alternate function pin type: output alternate function: reset output for downstream port 3 gpio[10] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p5rstn alternate function pin type: output alternate function: reset output for downstream port 5 signal type name/description apwrdisn i auxiliary power disable input. when this pin is active, it disables the device from using auxiliary power supply. cclkds i common clock downstream. the assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.this bit is used as the initial value of the slot clock configuration bit in all of the link status registers for downstream ports. the value may be override by modifying the sclk bit in the downstream port?s pcielsts register. cclkus i common clock upstream. the assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. this bit is used as the initial value of the slot clock configuration bit in the link status register for the upstream port. the value may be overridden by modifying the sclk bit in the pa_pcielsts register. msmbsmode i master smbus slow mode. the assertion of this pin indicates that the master smbus should operate at 100 khz instead of 400 khz. this value may not be overridden. perstn i fundamental reset. assertion of this signal resets all logic inside the pes8t5a and initiates a pci express fundamental reset. table 5 system pins (part 1 of 2) signal type name/description table 4 general purpose i/o pins (part 2 of 2)
7 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information rsthalt i reset halt. when this signal is asserted during a pci express fundamental reset, the pes8t5a executes the reset procedure and remains in a reset state with the master and slave smbuses active. this allows software to read and write registers internal to the device before normal device opera- tion begins. the device exits the reset state when the rsthalt bit is cleared in the pa_swctl register by an smbus master. swmode[2:0] i switch mode. these configuration pins determine the pes8t5a switch operating mode. 0x0 - normal switch mode 0x1 - normal switch mode with serial eeprom initialization 0x2 - through 0xf reserved waken i/o wake input/output. the waken signal is an input or output. the waken signal input/output selection can be made through the wakedir bit setting in the wakeupcntl register. signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board table 6 test pins signal type name/description v dd core i core vdd. power supply for core logic. v dd io i i/o vdd. lvttl i/o buffer power supply. v dd pe i pci express digital power. pci express digital power used by the digital power of the serdes. v dd ape i pci express analog power. pci express analog power used by the pll and bias generator. v tt pe i pci express termination power. v ss i ground. table 7 power and ground pins signal type name/description table 5 system pins (part 2 of 2)
8 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information pin characteristics note: some input pads of the pes8t5a do not contain internal pull- ups or pull-downs. unused inputs should be tied off to appropriate levels. this is especially critical for unused control signal i nputs which, if left floating, could adversely affect operation. also, any input pin left floating can cause a slight in crease in power consumption. function pin name type buffer i/o type internal resistor notes pci express inter- face pe0rn[1:0] i cml serial link pe0rp[1:0] i pe0tn[1:0] o pe0tp[1:0] o pe2rn[0] i pe2rp[0] i pe2tn[0] o pe2tp[0] o pe3rn[0] i pe3rp[0] i pe3tn[0] o pe3tp[0] o pe4rn[0] i pe4rp[0] i pe4tn[0] o pe4tp[0] o pe5rn[0] i pe5rp[0] i pe5tn[0] o pe5tp[0] o perefclkn i lvpecl/ cml diff. clock input refer totable 9 perefclkp i refclkm i lvttl input pull-down smbus msmbaddr[4:1] i lvttl input pull-up msmbclk i/o sti 1 msmbdat i/o sti ssmbaddr[5,3:1] i input pull-up ssmbclk i/o sti ssmbdat i/o sti general purpose i/o gpio[10:0] i/o lvttl high drive pull-up table 8 pin characteristics (part 1 of 2)
9 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information system pins apwrdisn i lvttl input pull-down cclkds i pull-up cclkus i pull-up msmbsmode i pull-down perstn i pull-up rsthalt i pull-down swmode[2:0] i pull-down waken i/o open-drain ejtag / jtag jtag_tck i lvttl sti pull-up jtag_tdi i sti pull-up jtag_tdo o jtag_tms i sti pull-up jtag_trst_n i sti pull-up 1. schmitt trigger input (sti) . function pin name type buffer i/o type internal resistor notes table 8 pin characteristics (part 2 of 2)
10 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information logic diagram ? pes8t5a figure 4 pes8t5a logic diagram perefclkp perefclkn jtag_tck gpio[10:0] 11 v dd core v dd i/o v dd pe v dd ape msmbaddr[4:1] msmbclk msmbdat 4 ssmbaddr[5,3:1] ssmbclk ssmbdat 4 cclkus rsthalt jtag_tdi jtag_tdo jtag_tms jtag_trst_n v ss swmode[2:0] 3 cclkds perstn refclkm msmbsmode v tt pe pe0rp[0] pe0rn[0] pe0rp[3] pe0rn[3] pe0tp[0] pe0tn[0] pe0tp[3] pe0tn[3] ... ... pe2rp] pe2rn] pe2tp pe2tn pe3rn pe3tp pe3tn pe4rp pe4rn pe4tp] pe4tn pe5rp] pe5rn] pe5tp pe5tn pes8t5a pe3rp waken reference clocks serdes input port 0 serdes input port 2 serdes input port 3 serdes input port 4 serdes input port 5 master smbus interface slave smbus interface system pins serdes output port 2 serdes output port 3 serdes output port 4 serdes output port 5 general purpose power/ground apwrdisn serdes output port 1 i/o
11 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information system clock parameters values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 13 and 14. ac timing characteristics parameter description min typical max unit perefclk refclk freq input reference clock frequency range 100 125 1 1. the input clock frequency will be either 100 or 125 mhz depending on signal refclkm. mhz refclk dc 2 2. clkin must be ac coupled. use 0.01 ? 0.1 f ceramic capacitors. duty cycle of input clock 40 50 60 % t r , t f rise/fall time of input clocks 0.2*rcui rcui 3 3. rcui (reference clock unit interval) refers to the reference clock period. v sw differential input voltage swing 4 4. ac coupling required. 0.6 1.6 v t jitter input clock jitter (cycle-to-cycle) 125 ps table 9 input clock requirements parameter description min typical max units pcie transmit t tx-rise , t tx-fall rise / fall time of txp, txn outputs 80 110 1 ps ui unit interval 399.88 400 400.12 ps t tx-max-jitter transmitter total jitter (peak-to-peak) 0.25 2 ui t tx-eye minimum tx eye width (1 - t tx-max-jitter )0.75 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.15 ui l tlat-10 transmitter data latency (for n=10) 9 11 bits l tlat-20 transmitter data latency (for n=20) 9 11 bits t tx-skew transmitter data skew between any 2 lanes 500 1300 ps t tx-idle-set-to- idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set 46ns t eiexit time to exit electrical idle (l0s) state into l0 12 16 ns t bten time from asserting beacon txen to beacon being trans- mitted on the lane 30 80 ns t rxdetecten pulse width of rxdetecten input 9.8 10 10.2 ns t rxdetect rxdetecten falling edge to rxdetect delay 1 2 ns pcie receive l rlat-10 recover data latency for n=10 28 29 bits l rlat-20 recover data latency for n=20 49 60 bits table 10 pcie ac timing characteristics (part 1 of 2)
12 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information figure 5 gpio ac timing waveform t rx-skew receiver data skew between any 2 lanes 20 ns t bddly beacon-activity on channel to detection of beacon 3 200 s t rx-idle_enter delay from detection of electrical idle condition on the channel to assertion of txidledetect output 10 20 ns t rx-idle_exit delay from detection of l0s to l0 transition to de-asser- tion of txidledetect output 510ns t rx-max-jitter receiver total jitter tolerance 0.65 ui t rx-eye minimum receiver eye width 0.35 ui t rx-eye-median-to- max jitter maximum time between jitter median and max deviation from median 0.325 ui 1. as measured between 20% and 80% points. will depend on package characteristics. 2. measured using pci express compliance pattern. 3. this is a function of beacon frequency. signal symbol reference edge min max unit timing diagram reference gpio gpio[10:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw_13b 2 2. the values for this symbol were determined by calculation, not by testing. none 50 ? ns see figure 5. table 11 gpio ac timing characteristics parameter description min typical max units table 10 pcie ac timing characteristics (part 2 of 2) tdo_13a tdo_13a tpw_13b extclk gpio (synchronous output) gpio (asynchronous input)
13 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information figure 6 jtag ac timing waveform signal symbol reference edge min max unit timing diagram reference jtag jtag_tck tper_16a none 25.0 50.0 ns see figure 6. thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, recommends that jtag_tms should be held at 1 while the signal applied at jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag _tck when jtag_tms is low, because the tap controller might go to either the run-test/idle state or stay in the test-logic-reset sta te. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 11.3 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ? 11.3 ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 12 jtag ac timing characteristics tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
14 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information recommended operating supply voltages power-up/power-down sequence this section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper func tionality. for the pes8t5a, the power-up sequence must be as follows: 1. v dd i/o ? 3.3v 2. v dd core, v dd pe, v dd ape ? 1.0v 3. v tt pe ? 1.5v when powering up, each voltage level must ramp and stabilize prio r to applying the next voltage in the sequence to ensure inter nal latch-up issues are avoided. there are no maximum time limitations in ramping to valid power levels. the power-down sequence must be in the reverse order of the power-up sequence. recommended operating temperature symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serdes lvpecl/cml 3.135 3.3 3.465 v v dd pe pci express digital power 0.9 1.0 1.1 v v dd ape pci express analog power 0.9 1.0 1.1 v v tt pe pci express serial data transmit termination voltage 1.425 1.5 1.575 v v ss common ground 0 0 0 v table 13 pes8t5a operating voltages grade temperature commercial 0 c to +70 c ambient table 14 pes8t5a operating temperatures
15 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information power consumption parameter typ. max. unit conditions i dd i/o tbd tbd ma t ambient = 25 o c max. values use the maximum volt- ages listed in table 13. typical val- ues use the typical voltages listed in that table. i dd core normal mode tbd tbd ma standby mode 1 1. all ports in d1 state. tbd ? ma i dd pe, tbd tbd ma i dd ape tbd tbd ma i tt pe tbd tbd ma power dissipation normal mode tbd tbd w standby mode 1 tbd ? w table 15 pes8t5a power consumption
16 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information dc electrical characteristics values based on systems running at recommended supply voltages, as shown in table 13. note: see table 8, pin characteristics, for a complete i/o listing. i/o type parameter description min 1 typ 1 max 1 unit conditions serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 mv v tx-de-ratio de-emphasized differential output voltage -3 -4 db v tx-dc-cm dc common mode voltage -0.1 1 3.7 v v tx-cm-acp rms ac peak common mode output volt- age 20 mv v tx-cm-dc- active-idle-delta abs delta of dc common mode voltage between l0 and idle 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 mv v tx-idle-diffp electrical idle diff peak output 20 mv v tx-rcv-detect voltage change during receiver detection 600 mv rl tx-diff transmitter differential return loss 12 db rl tx-cm transmitter common mode return loss 6 db z tx-deff-dc dc differential tx impedance 80 100 120 z ose single ended tx impedance 40 50 60 transmitter eye diagram tx eye height (de-emphasized bits) 505 650 mv transmitter eye diagram tx eye height (transition bits) 800 950 mv pcie receive v rx-diffp-p differential input voltage (peak-to-peak) 175 1200 mv v rx-cm-ac receiver common-mode voltage for ac coupling 150 mv rl rx-diff receiver differential return loss 15 db rl rx-cm receiver common mode return loss 6 db z rx-diff-dc differential input impedance (dc) 80 100 120 z rx-comm-dc single-ended input impedance 40 50 60 z rx-comm-high- z-dc powered down input common mode impedance (dc) 200k 350k v rx-idle-det- diffp-p electrical idle detect threshold 65 175 mv pcie refclk c in input capacitance 1.5 ? pf table 16 dc electrical characteristics (part 1 of 2)
17 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information other i/os low drive output i ol ?2.5?ma v ol = 0.4v i oh ?-5.5?ma v oh = 1.5v high drive output i ol ? 12.0 ? ma v ol = 0.4v i oh ?-20.0?ma v oh = 1.5v schmitt trig- ger input (sti) v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd io + 0.5 v? input v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd io + 0.5 v? capacitance c in ??8.5pf ? leakage inputs ? ? + 10 av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 av dd i/o (max) 1. minimum, typical, and maximum values meet the requirements under pci specification 1.1. i/o type parameter description min 1 typ 1 max 1 unit conditions table 16 dc electrical characteristics (part 2 of 2)
18 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information package pinout ? 196-bga signal pinout for pes8t5a the following table lists the pin numbers and signal names for the pes8t5a device. pin function alt pin function alt pin function alt pin function alt a1 v ss c7 v dd ape e13 v dd core h5 v ss a2 pe0rp03 c8 v dd ape e14 v ss h6 v dd core a3 v ss c9 v tt pe f1 msmbdat h7 v dd core a4 pe0tn03 c10 cclkds f2 ssmbaddr_2 h8 v ss a5 pe0tp02 c11 v ss f3 ssmbaddr_5 h9 v ss a6 v ss c12 v dd io f4 v dd io h10 v dd core a7 pe0rn02 c13 v ss f5 v ss h11 v dd core a8 pe0rn01 c14 swmode_0 f6 v dd core h12 gpio_05 a9 v ss d1 ssmbclk f7 v dd core h13 gpio_03 1 a10 pe0tp01 d2 ssmbdat f8 v ss h14 gpio_02 a11 pe0tn00 d3 v ss f9 v dd core j1 jtag_tdo a12 v ss d4 v dd io f10 v dd core j2 jtag_trst_n a13 pe0rp00 d5 v dd core f11 v dd io j3 jtag_tms a14 v ss d6 v dd core f12 gpio_00 1 j4 v dd core b1 v ss d7 v dd pe f13 perstn j5 v ss b2 pe0rn03 d8 v dd pe f14 v ss j6 v dd core b3 v ss d9 v dd core g1 msmbaddr_4 j7 v ss b4 pe0tp03 d10 v dd io g2 msmbclk j8 v dd core b5 pe0tn02 d11 v dd core g3 v dd io j9 v dd core b6 v ss d12 v ss g4 v ss j10 v ss b7 pe0rp02 d13 swmode_2 g5 v dd core j11 v dd io b8 pe0rp01 d14 swmode_1 g6 v ss j12 v dd io b9 v ss e1 ssmbaddr_1 g7 v ss j13 gpio_06 b10 pe0tn01 e2 ssmbaddr_3 g8 v dd core j14 gpio_04 1 b11 pe0tp00 e3 v dd io g9 v ss k1 jtag_tdi b12 v ss e4 v dd core g10 v ss k2 v dd io b13 pe0rn00 e5 v ss g11 v ss k3 v dd ape b14 v ss e6 v ss g12 v dd io k4 v ss c1 waken e7 v ss g13 gpio_01 1 k5 v dd core c2 apwrdisn e8 v ss g14 rsthalt k6 v ss c3 cclkus e9 v ss h1 msmbaddr_1 k7 v ss c4 v ss e10 v dd core h2 msmbaddr_2 k8 v ss c5 v ss e11 v ss h3 msmbaddr_3 k9 v ss c6 v tt pe e12 v dd io h4 v dd core k10 v ss table 17 pes8t5a 196-pin signal pin-out (part 1 of 2)
19 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information alternate signal functions k11 v dd core l12 v ss m13 msmbsmode n14 pe5rn00 k12 v ss l13 gpio_10 1 m14 v ss p1 perefclkp k13 gpio_08 l14 gpio_09 1 n1 perefclkn p2 v ss k14 gpio_07 1 m1 v ss n2 v ss p3 pe2rp00 l1 jtag_tck m2 v dd core n3 pe2rn00 p4 v ss l2 v ss m3 v dd core n4 v ss p5 pe2tn00 l3 v ss m4 v ss n5 pe2tp00 p6 pe3tp00 l4 v dd io m5 v dd io n6 pe3tn00 p7 v ss l5 v dd core m6 v tt pe n7 v ss p8 pe3rp00 l6 v dd core m7 v dd ape n8 pe3rn00 p9 pe4rn00 l7 v dd pe m8 v dd ape n9 pe4rp00 p10 v ss l8 v dd pe m9 v tt pe n10 v ss p11 pe4tp00 l9 v dd core m10 v dd io n11 pe4tn00 p12 pe5tn00 l10 v dd core m11 v dd io n12 pe5tp00 p13 v ss l11 v ss m12 refclkm n13 v ss p14 pe5rp00 pin gpio alternate f12 gpio_00 p2rstn g13 gpio_01 p4rstn h14 gpio_02 ioexpintn0 h13 gpio_03 ioexpintn1 j14 gpio_04 ioexpintn2 k14 gpio_07 gpen l14 gpio_09 p3rstn l13 gpio_10 p5rstn table 18 pes8t5a alternate signal functions pin function alt pin function alt pin function alt pin function alt table 17 pes8t5a 196-pin signal pin-out (part 2 of 2)
20 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information power pins v dd core v dd core v dd io v dd pe v dd ape v tt pe d5 h10 c12 d7 c7 c6 d6 h11 d4 d8 c8 c9 d9 j4 d10 l7 k3 m6 d11 j6 e3 l8 m7 m9 e4 j8 e12 m8 e10 j9 f4 e13 k5 f11 f6 k11 g3 f7 l5 g12 f9 l6 j11 f10 l9 j12 g5 l10 k2 g8 m2 l4 h4 m3 m5 h6 m10 h7 m11 table 19 pes8t5a power pins
21 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information ground pins v ss v ss v ss v ss a1 d3 g10 l3 a3 d12 g11 l11 a6 e5 h5 l12 a9 e6 h8 m1 a12 e7 h9 m4 a14 e8 j5 m14 b1 e9 j7 n2 b3 e11 j10 n4 b6 e14 k4 n7 b9 f5 k6 n10 b12 f8 k7 n13 b14 f14 k8 p2 c4 g4 k9 p4 c5 g6 k10 p7 c11 g7 k12 p10 c13 g9 l2 p13 table 20 pes8t5a ground pins
22 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information signals listed alphabetically signal name i/o type location signal category apwrdisn i c2 system cclkds i c10 cclkus i c3 gpio_00 i/o f12 general purpose input/output gpio_01 i/o g13 gpio_02 i/o h14 gpio_03 i/o h13 gpio_04 i/o j14 gpio_05 i/o h12 gpio_06 i/o j13 gpio_07 i/o k14 gpio_08 i/o k13 gpio_09 i/o l14 gpio_10 i/o l13 jtag_tck i l1 jtag jtag_tdi i k1 jtag_tdo o j1 jtag_tms i j3 jtag_trst_n i j2 msmbaddr_1 i h1 smbus msmbaddr_2 i h2 msmbaddr_3 i h3 msmbaddr_4 i g1 msmbclk i/o g2 msmbdat i/o f1 msmbsmode i m13 system pe0rn00 i b13 pci express pe0rn01 i a8 pe0rn02 i a7 pe0rn03 i b2 pe0rp00 i a13 pe0rp01 i b8 pe0rp02 i b7 pe0rp03 i a2 table 21 pes8t5a alphabetical signal list (part 1 of 3)
23 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information pe0tn00 o a11 pci express (cont.) pe0tn01 o b10 pe0tn02 o b5 pe0tn03 o a4 pe0tp00 o b11 pe0tp01 o a10 pe0tp02 o a5 pe0tp03 o b4 pe2rn00 i n3 pe2rp00 i p3 pe2tn00 o p5 pe2tp00 o n5 pe3rn00 i n8 pe3rp00 i p8 pe3tn00 o n6 pe3tp00 o p6 pe4rn00 i p9 pe4rp00 i n9 pe4tn00 o n11 pe4tp00 o p11 pe5rn00 i n14 pe5rp00 i p14 pe5tn00 o p12 pe5tp00 o n12 perefclkn i n1 perefclkp i p1 perstn i f13 system refclkm i m12 pci express rsthalt i g14 system ssmbaddr_1 i e1 smbus ssmbaddr_2 i f2 ssmbaddr_3 i e2 ssmbaddr_5 i f3 ssmbclk i/o d2 smbus ssmbdat i/o d1 signal name i/o type location signal category table 21 pes8t5a alphabetical signal list (part 2 of 3)
24 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information swmode_0 i c14 system swmode_1 i d14 swmode_2 i d13 v dd core, v dd ape, v dd io, v dd pe , v tt pe see table 19 for a listing of power pins. v ss see table 20 for a listing of ground pins. signal name i/o type location signal category table 21 pes8t5a alphabetical signal list (part 3 of 3)
25 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information pes8t5a pinout ? top view 123456 7 8 9 10 11 12 13 14 vss (ground) v dd core (power) v dd i/o (power) v tt pe (power) v dd pe (power) v dd ape (power) signals a b c d e f g h j k l m n p x a b c d e f g h j k l m n p 123456 7 8 9 10 11 12 13 14 x x xx
26 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information pes8t5a package drawing ? 196-pin bc196/bcg196
27 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information pes8t5a package drawing ? page two
28 of 29 september 7, 2007 idt 89hpes8t5a data sheet advance information revision history august 16, 2007 : initial publication of advanced data sheet. september 7, 2007 : added power-up/power down sequence.
29 of 29 september 7, 2007 idt 89hpes8t5a data sheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com advance information for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ? ordering information valid combinations 89HPES8T5AZABC 196-pin bc196 package, commercial temperature 89HPES8T5AZABCg 196-pin green bcg196 package, commercial temperature nn aaaa nana aa a operating voltage device family product package temp range h blank commercial temperature (0c to +70c ambient) product family 89 serial switching product bc196 196-ball cabga bc 8t5a 8-lane, 5-port 1.0v +/- 0.1v core voltage detail pci express switch pes legend a = alpha character n = numeric character bcg196 196-ball cabga, green bcg aa device revision za za revision

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